CD4516, clocked by NE555, step 4 in 4

[Marcus]

I build a little circuit where a CD4516 (4 bit u/d counter with reset, preset, C-in e C-out) is clocked by a NE555 configured as astable.
The NE555 frequency is set to 0.5 Hz, 50% duty cicle (just for the sperimental version of the circuit)
Another NE555 (hereinafter NE555[m])  is used in monostable configuration to drive the Reset/Preset input of the CD4516
The CD4516 is configured as follow:
- C-In -> VSS (GND)
- P0, P1, P2, P3 to VDD
- Reset -> negated output of the NE555[m]
- Preset -> output of the NE555[m]
- Q0, Q1, Q2, Q3 -> to green leds via a 560 ohm resistor
- C-Out to a logic control that set the reset pin NE555  to GND (to stop the NE555)
- U/D to VSS (the counter must count down)

Supply is 12VCC

Initial condition: the NE555[m] is in the stable state (pin 3 is GND): negating the output, the Reset pin of the CD4516 is in the Reset condition: Q0, Q1, Q2 and Q3 are low the C-Out is low too; a logic control keep the NE555 reset pin in low state so no clock signal can drive the CD4516.

Step 1
triggering the NE555[m], his output goes hi for 1/2 second: the reset pin of the CD4516 goes low and the preset pin goes hi so the Q0, Q1, Q2 and Q3 goes hi and the C-out pin goes hi too.

Step 2
the NE555[m] back to stable condition: a logic control keep low the reset pin of the CD4516, while the preset pin goes low and the NE555 reset pin goes hi, let it to start the clock signal that drive the CD4516 clock input

Step 3
the CD4516 starting count down: but instead of count from 15, 14, 13 ... 0 it count 11, 7, 4, 1, 0 (??)

Step 4
disconnect the output of the NE555 from the CD4516 clock input

Step 5
connect a free-in-air wire to the CD4516 clock input

Step 6
trigger NE555[m] to reset/preset the CD4516: it is waiting for clock signal to start the count-down

Step 7
alternatively connect the free-in-air wire to VSS and VDD: the CD4516 output count from 15 to 0 step -1 each time i connect the free-in-air wire to VDD
 
The questions are:
1) Where is the Step 3 issue?
2) Where is the difference from drive the CD4516 clock input by the NE555 output and the VDD -> VSS -> VDD cicle manually simulated?

Every reply appreciated

Regards

[kam]

it would be good to post a schematic. I really could not understand the connection.

[Marcus]

OK. The circuit is currently mounted on a breadboard. I've no the global schemas but only some "sections" on some paper sheet.
Can you suggest me a free software designer tool that allow me to include component as C, R, IC?
The only design tool that I use is "LTSpiece IV" but it is not suitable for circuit schemas that include IC 

[kam]

free PCB

but also, you can make a dirty schematic with the windows paint....

[Marcus]

No Free PCB, no Paint, simple TinyCAD

find attached the schema

I don't put the passive components values: if them are essential I re-post the schema with that values.

[Marcus]

In this afternoon I do further tests

Test A - clocking the CD4516 manually, moving the free-in-air wire from VDD to VSS and viceversa; note that "fia" stand for "free-in-air" condition of the wire.


   Clock   |Count | Q0 | Q1 | Q2 | Q3 | Cout |
-----------+------+----+----+----+----+------+
fia -> VDD |   15 |  1 |  1 |  1 |  1 |    1 |
VDD -> fia |   15 |  1 |  1 |  1 |  1 |    1 |
fia -> VSS |   15 |  1 |  1 |  1 |  1 |    1 |
VSS -> fia |   15 |  1 |  1 |  1 |  1 |    1 |
fia -> VDD |   14 |  0 |  1 |  1 |  1 |    1 |
VDD -> fia |   14 |  0 |  1 |  1 |  1 |    1 |
fia -> VSS |   14 |  0 |  1 |  1 |  1 |    1 |
VSS -> fia |   14 |  0 |  1 |  1 |  1 |    1 |
fia -> VDD |   13 |  1 |  0 |  1 |  1 |    1 |
VDD -> fia |   13 |  1 |  0 |  1 |  1 |    1 |
fia -> VSS |   13 |  1 |  0 |  1 |  1 |    1 |
VSS -> fia |   13 |  1 |  0 |  1 |  1 |    1 |
fia -> VDD |   12 |  0 |  0 |  1 |  1 |    1 |
VDD -> fia |   12 |  0 |  0 |  1 |  1 |    1 |
fia -> VSS |   12 |  0 |  0 |  1 |  1 |    1 |
VSS -> fia |   12 |  0 |  0 |  1 |  1 |    1 |
fia -> VDD |   11 |  1 |  1 |  0 |  1 |    1 |
VDD -> fia |   11 |  1 |  1 |  0 |  1 |    1 |
fia -> VSS |   11 |  1 |  1 |  0 |  1 |    1 |
VSS -> fia |   11 |  1 |  1 |  0 |  1 |    1 |
fia -> VDD |   10 |  0 |  1 |  0 |  1 |    1 |
VDD -> fia |   10 |  0 |  1 |  0 |  1 |    1 |
fia -> VSS |   10 |  0 |  1 |  0 |  1 |    1 |
VSS -> fia |   10 |  0 |  1 |  0 |  1 |    1 |
fia -> VDD |    9 |  1 |  0 |  0 |  1 |    1 |
VDD -> fia |    9 |  1 |  0 |  0 |  1 |    1 |
fia -> VSS |    9 |  1 |  0 |  0 |  1 |    1 |
VSS -> fia |    9 |  1 |  0 |  0 |  1 |    1 |
fia -> VDD |    8 |  0 |  0 |  0 |  1 |    1 |
VDD -> fia |    8 |  0 |  0 |  0 |  1 |    1 |
fia -> VSS |    8 |  0 |  0 |  0 |  1 |    1 |
VSS -> fia |    8 |  0 |  0 |  0 |  1 |    1 |
fia -> VDD |    7 |  1 |  1 |  1 |  0 |    1 |
VDD -> fia |    7 |  1 |  1 |  1 |  0 |    1 |
fia -> VSS |    7 |  1 |  1 |  1 |  0 |    1 |
VSS -> fia |    7 |  1 |  1 |  1 |  0 |    1 |
fia -> VDD |    6 |  0 |  1 |  1 |  0 |    1 |
VDD -> fia |    6 |  0 |  1 |  1 |  0 |    1 |
fia -> VSS |    6 |  0 |  1 |  1 |  0 |    1 |
VSS -> fia |    6 |  0 |  1 |  1 |  0 |    1 |
fia -> VDD |    5 |  1 |  0 |  1 |  0 |    1 |
VDD -> fia |    5 |  1 |  0 |  1 |  0 |    1 |
fia -> VSS |    5 |  1 |  0 |  1 |  0 |    1 |
VSS -> fia |    5 |  1 |  0 |  1 |  0 |    1 |
fia -> VDD |    4 |  0 |  0 |  1 |  0 |    1 |
VDD -> fia |    4 |  0 |  0 |  1 |  0 |    1 |
fia -> VSS |    4 |  0 |  0 |  1 |  0 |    1 |
VSS -> fia |    4 |  0 |  0 |  1 |  0 |    1 |
fia -> VDD |    3 |  1 |  1 |  0 |  0 |    1 |
VDD -> fia |    3 |  1 |  1 |  0 |  0 |    1 |
fia -> VSS |    3 |  1 |  1 |  0 |  0 |    1 |
VSS -> fia |    3 |  1 |  1 |  0 |  0 |    1 |
fia -> VDD |    2 |  0 |  1 |  0 |  0 |    1 |
VDD -> fia |    2 |  0 |  1 |  0 |  0 |    1 |
fia -> VSS |    2 |  0 |  1 |  0 |  0 |    1 |
VSS -> fia |    2 |  0 |  1 |  0 |  0 |    1 |
fia -> VDD |    1 |  1 |  0 |  0 |  0 |    1 |
VDD -> fia |    1 |  1 |  0 |  0 |  0 |    1 |
fia -> VSS |    1 |  1 |  0 |  0 |  0 |    1 |
VSS -> fia |    1 |  1 |  0 |  0 |  0 |    1 |
fia -> VDD |    0 |  0 |  0 |  0 |  0 |    0 |
VDD -> fia |    0 |  0 |  0 |  0 |  0 |    0 |
fia -> VSS |    0 |  0 |  0 |  0 |  0 |    0 |
VSS -> fia |    0 |  0 |  0 |  0 |  0 |    0 |
fia -> VDD |    1 |  1 |  1 |  1 |  1 |    1 |
           .      .    .    .    .    .      .
ecc.


Test B: CD4516 clocked by NE555 (some time has this behavior); note that the simbol in the column "out" of NE555 stands for raising edge ( _/ ) and falling edge ( \_ )


------------------+-----------------------------------+
        NE555     |               CD4516              |
----------+-------+--------+----+----+----+----+------+-------
   out    | reset | preset | Q0 | Q1 | Q2 | Q3 | Cout | Count
----------|-------+--------+----+----+----+----+------+-------
   _ 0    |   0   |    1   |  1 |  1 |  1 |  1 |    1 |  15
 _/  _    |   1   |    0   |  1 |  0 |  1 |  1 |    1 |  13
   _  \_  |   1   |    0   |  1 |  0 |  1 |  1 |    1 |  13
 _/  _    |   1   |    0   |  0 |  0 |  1 |  1 |    1 |  12
   _  \_  |   1   |    0   |  0 |  0 |  1 |  1 |    1 |  12
 _/  _    |   1   |    0   |  1 |  1 |  0 |  1 |    1 |  11
   _  \_  |   1   |    0   |  1 |  1 |  0 |  1 |    1 |  11
 _/  _    |   1   |    0   |  0 |  1 |  0 |  1 |    1 |  10
   _  \_  |   1   |    0   |  0 |  1 |  0 |  1 |    1 |  10
 _/  _    |   1   |    0   |  1 |  0 |  0 |  1 |    1 |   9
   _  \_  |   1   |    0   |  1 |  0 |  0 |  1 |    1 |   9
 _/  _    |   1   |    0   |  0 |  0 |  0 |  1 |    1 |   8
   _  \_  |   1   |    0   |  0 |  0 |  0 |  1 |    1 |   8
 _/  _    |   1   |    0   |  1 |  1 |  1 |  0 |    1 |   7
   _  \_  |   1   |    0   |  1 |  1 |  1 |  0 |    1 |   7
 _/  _    |   1   |    0   |  0 |  1 |  1 |  0 |    1 |   6
   _  \_  |   1   |    0   |  0 |  1 |  1 |  0 |    1 |   6
 _/  _    |   1   |    0   |  1 |  0 |  1 |  0 |    1 |   5
   _  \_  |   1   |    0   |  1 |  0 |  1 |  0 |    1 |   5
 _/  _    |   1   |    0   |  0 |  0 |  1 |  0 |    1 |   4
   _  \_  |   1   |    0   |  0 |  0 |  1 |  0 |    1 |   4
 _/  _    |   1   |    0   |  1 |  1 |  0 |  0 |    1 |   3
   _  \_  |   1   |    0   |  1 |  1 |  0 |  0 |    1 |   3
 _/       |   1   |    0   |  0 |  0 |  0 |  0 |    0 |   0
     0    |   0   |    0   |  0 |  0 |  0 |  0 |    0 |   0
----------+-------+--------+----+----+----+----+------+-------


Test C: same condition of Test B, but different behaviour

------------------+-----------------------------------+
        NE555     |               CD4516              |
----------+-------+--------+----+----+----+----+------+-------
   out    | reset | preset | Q0 | Q1 | Q2 | Q3 | Cout | Count
----------|-------+--------+----+----+----+----+------+-------
   _ 0    |   0   |    1   |  1 |  1 |  1 |  1 |    1 |  15
 _/  _    |   1   |    0   |  1 |  0 |  1 |  1 |    1 |  13
   _  \_  |   1   |    0   |  1 |  0 |  1 |  1 |    1 |  13
 _/  _    |   1   |    0   |  1 |  1 |  0 |  1 |    1 |  11
   _  \_  |   1   |    0   |  1 |  1 |  0 |  1 |    1 |  11
 _/  _    |   1   |    0   |  1 |  1 |  1 |  0 |    1 |   7
   _  \_  |   1   |    0   |  1 |  1 |  1 |  0 |    1 |   7
 _/  _    |   1   |    0   |  1 |  1 |  0 |  0 |    1 |   3
   _  \_  |   1   |    0   |  1 |  1 |  0 |  0 |    1 |   3
 _/       |   1   |    0   |  0 |  0 |  0 |  0 |    0 |   0
     0    |   0   |    0   |  0 |  0 |  0 |  0 |    0 |   0
----------+-------+--------+----+----+----+----+------+-------

[kam]

i cannot get what is the purpose of the or-and-and gates on left side under the 555[m]. I can only guess that you want to make a start-stop for the counter, is that right? I mean, you want to press the START and one shot is send (555 makes the one shot) to the gates, which are supposed to "lock" to start? And only unlock when you press the reset? Is this right? If yes, then you need to replace the 555[m] and these gates with a flip-flop, toggle or SR

[Marcus]

Yes Kam, in few words the pourpose is what you have described, but let me to be more accurated: all the gates under the NE555[m] do the following tasks:
1) prepare the signal for the CD4516 reset/preset
2) set the NE555[m] reset to 0 after it has produced the 1st shot: any subsequent START will be ignored (unless you press the RESET)
3) the NE555 is reset (stop the astable cicle) when the CD4516 carry out is zero (cicle completed) and the reset input is zero (this last, means that the carry out is zero not for external reset, but because the counter ha completed the cicle)

An SR latch has the 1 - 1 or the 0 - 0 issue (depending respectively if the SR is implemented by NAND gates or by NOR gates): what happen if I press START and RESET at the same time?
A Toggle flip flop must be clocked and a it has only 1 input, while I need two: START and RESET (the T flip flop is a JK flip flop where J and K is shorted together, and the it need a clock).

In other words:
a) when START is pushed, it make serveral action (not only start the NE555 astable cicle)
b) when RESET is pushed, it reset the NE555[m], CD4516 and NE555 initial condition
c) the NE555 astable cicle can ben stopped by the CD4516 carry out signal or pushing the RESET.
This make the SR o T (J/K) flip flop not suitable for my project.

Anyway, the issue is not in the gate net: it behavior is as required by the design; the focus would be point on the different behavior of the CD4516: one when it be clocked "manually", and the other(s) when it be clocked by the NE555.

I hope this make my question more clear.

Thank you in adavance

[Marcus]

I put a NPN transistor between the NE555 out and the CD4516 clock-in. The NPN transistor simply negate the NE555 out making the clock signal starting from low-level immediately after the CD4516 preset goes low. Then, The NE555 out goes low and CD4516 clock-in catch the first raising edge.
The CD4516 has a particulary propagation delay, issued by the preset state: so, while the preset goes low, the clock-in must not be in hi-level. The first clock raising edge after preset, must issued when the preset is allready at low level.