A BCD coded rate multiplier can be a nice way to derive a signal whose frequency is settable to an input frequency multiplied by 0.1, 0.2 and so forth to 0.9 of the input frequency, but the periodicity of the rate multiplier output can be inconvenient. You can get the right number of pulses per unit of time, but at the price of having to deal with missing pulses for certain division ratios.
However, if you can clock the rate multiplier fast enough, following the rate multiplier output with a string of divide-by-two stages tends to smooth out the periodicity issue.
In this sketch, the shaded areas are only shaded to make it easier to see the full cycles of frequency division and the periodicity improvements.
For each division factor, the top line is the output of the rate multiplier itself. Then, each line below is the output of a divide-by-two. The results for three divide-by-two stages are shown with shading.