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CD4000 Serie IC Pinouts

 CD4000 Serie   74 Serie   Op amp   Opt   

4001

Quad 2-input NOR gates.
    +---+--+---+             +---+---*---+           ___
 1A |1  +--+ 14| VCC         | A | B |/Y |      /Y = A+B
 1B |2       13| 4B          +===+===*===+
/1Y |3       12| 4A          | 0 | 0 | 1 |
/2Y |4  4001 11| /4Y         | 0 | 1 | 0 |
 2A |5       10| /3Y         | 1 | 0 | 0 |
 2B |6        9| 3B          | 1 | 1 | 0 |
GND |7        8| 3A          +---+---*---+
    +----------+

4002

Dual 4-input NOR gates.
    +---+--+---+             +---+---+---+---*---+       _________
/1Y |1  +--+ 14| VCC         | A | B | C | D |/Y |  /Y = (A+B+C+D)
 1A |2       13| /2Y         +===+===+===+===*===+
 1B |3       12| 2D          | 0 | 0 | 0 | 0 | 1 |
 1C |4  4002 11| 2C          | 0 | 0 | 0 | 1 | 0 |
 1D |5       10| 2B          | 0 | 0 | 1 | X | 0 |
    |6        9| 2A          | 0 | 1 | X | X | 0 |
GND |7        8|             | 1 | X | X | X | 0 |
    +----------+             +---+---+---+---*---+

4006

Dual 4-bit and dual 5-bit serial-in serial-out shift registers with common clock.
     +---+--+---+
  1D |1  +--+ 14| VCC
/1Q4 |2       13| 1Q4
 CLK |3       12| 2Q5
  2D |4  4006 11| 2Q4
  3D |5       10| 3Q4
  4D |6        9| 4Q5
 GND |7        8| 4Q4
     +----------+

4007

Dual complementary CMOS pair and unbuffered inverter.
For use as simple inverters, connect 1pS=3pS=VCC, 1nS=3nS=GND, 1pD=1nD=/1Y and 2pD=2nD=/2Y.
     +---+--+---+
 1pD |1  +--+ 14| VCC
 1pS |2       13| 2pD
  1G |3       12| /3Y
 1nS |4  4007 11| 3pS
 1nD |5       10| 3G
  2G |6        9| 3nS
 GND |7        8| 2nD
     +----------+

4008

4-bit binary full adder with fast carry.
    +---+--+---+
 A3 |1  +--+ 16| VCC         S=A+B+CIN
 B2 |2       15| B3
 A2 |3       14| CO
 B1 |4       13| S3
 A1 |5  4008 12| S2
 B0 |6       11| S1
 A0 |7       10| S0
GND |8        9| CI
    +----------+

4009

Hex inverters with level shifted outputs.
VDD may not be lower than VCC.
    +---+--+---+             +---*---+               _
VCC |1  +--+ 16| VDD         | A |/Y |          /Y = A
/Y1 |2       15| /Y6         +===*===+
 A1 |3       14| A6          | 0 | 1 |
/Y2 |4       13|             | 1 | 0 |
 A2 |5  4009 12| /Y5         +---*---+
/Y3 |6       11| A5
 A3 |7       10| /Y4
GND |8        9| A4
    +----------+

4010

Hex buffers with level shifted outputs.
VDD may not be lower than VCC.
    +---+--+---+             +---*---+
VCC |1  +--+ 16| VDD         | A | Y |           Y = A
 Y1 |2       15| Y6          +===*===+
 A1 |3       14| A6          | 0 | 0 |
 Y2 |4       13|             | 1 | 1 |
 A2 |5  4010 12| Y5          +---*---+
 Y3 |6       11| A5
 A3 |7       10| Y4
GND |8        9| A4
    +----------+

4011

Quad 2-input NAND gates.
    +---+--+---+             +---+---*---+           __
 1A |1  +--+ 14| VCC         | A | B |/Y |      /Y = AB
 1B |2       13| 4B          +===+===*===+
/1Y |3       12| 4A          | 0 | 0 | 1 |
/2Y |4  4011 11| /4Y         | 0 | 1 | 1 |
 2A |5       10| /3Y         | 1 | 0 | 1 |
 2B |6        9| 3B          | 1 | 1 | 0 |
GND |7        8| 3A          +---+---*---+
    +----------+

4012

Dual 4-input NAND gates.
    +---+--+---+             +---+---+---+---*---+        ____
/1Y |1  +--+ 14| VCC         | A | B | C | D |/Y |   /Y = ABCD
 1A |2       13| /2Y         +===+===+===+===*===+
 1B |3       12| 2D          | 0 | X | X | X | 1 |
 1C |4  4012 11| 2C          | 1 | 0 | X | X | 1 |
 1D |5       10| 2B          | 1 | 1 | 0 | X | 1 |
    |6        9| 2A          | 1 | 1 | 1 | 0 | 1 |
GND |7        8|             | 1 | 1 | 1 | 1 | 0 |
    +----------+             +---+---+---+---*---+

4013

Dual D flip-flop with set and reset.
      +---+--+---+           +---+---+---+---*---+---+
   1Q |1  +--+ 14| VCC       | D |CLK|SET|RST| Q |/Q |
  /1Q |2       13| 2Q        +===+===+===+===*===+===+
 1CLK |3       12| /2Q       | X | X | 0 | 1 | 0 | 1 |
 1RST |4  4013 11| 2CLK      | X | X | 1 | 0 | 1 | 0 |
   1D |5       10| 2RST      | X | X | 1 | 1 | 1 | 1 |
 1SET |6        9| 2D        | 0 | / | 0 | 0 | 0 | 1 |
  GND |7        8| 2SET      | 1 | / | 0 | 0 | 1 | 1 |
      +----------+           | X |!/ | 0 | 0 | - | - |
                             +---+---+---+---*---+---+

4014

8-bit parallel-in serial-out shift register with three parallel outputs.
    +---+--+---+
 P7 |1  +--+ 16| VCC
 Q5 |2       15| P6
 Q7 |3       14| P5
 P3 |4       13| P4
 P2 |5  4014 12| Q6
 P1 |6       11| D
 P0 |7       10| CLK
GND |8        9| LD//SH
    +----------+

4015

Dual 4-bit serial-in parallel-out shift register with asynchronous reset.
     +---+--+---+
2CLK |1  +--+ 16| VCC
 2Q3 |2       15| 2D
 1Q2 |3       14| 2RST
 1Q1 |4       13| 2Q0
 1Q0 |5  4015 12| 2Q1
1RST |6       11| 2Q2
  1D |7       10| 1Q3
 GND |8        9| 1CLK
     +----------+

4016

Quad analog switches.
     +---+--+---+
  1X |1  +--+ 14| VCC
  1Y |2       13| 1EN
  2Y |3       12| 4EN
  2X |4  4016 11| 4X
 2EN |5  4066 10| 4Y
 3EN |6        9| 3Y
 GND |7        8| 3X
     +----------+

4017

4-bit asynchronous decade counter with fully decoded outputs, reset and both active high and active low clocks.

The two CLK inputs are ANDed together, so that either can be used as clock or clock enable.

    +---+--+---+
 Q5 |1  +--+ 16| VCC
 Q1 |2       15| RST
 Q0 |3       14| CLK1
 Q2 |4       13| /CLK2
 Q6 |5  4017 12| RCO
 Q7 |6       11| Q9
 Q3 |7       10| Q4
GND |8        9| Q8
    +----------+

4018

5-stage (divide by 2,4,6,8 or 10) Johnson counter with preset inputs.
    +---+--+---+
  D |1  +--+ 16| VCC
 P1 |2       15| RST
 P2 |3       14| CLK
/Q2 |4       13| /Q5
/Q1 |5  4018 12| P5
/Q3 |6       11| /Q4
 P3 |7       10| PE
GND |8        9| P4
    +----------+



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