  24 February 2009
Author: Giorgos Lazaridis
BJT Transistor theory

Output Signal Clipping

An amplified AC signal is subject to clipping if it exceeds some specific levels. These levels are determined by the DC and AC load lines and the operation point Q. To explain why the output clipping occurs, we will first work with the simplest case in which the DC load line is the same as the AC load line. This happens (as we explained before) if the transistor output has no load, or if the load has very high resistance, about ten times higher than the collector's resistor RC. Suppose that we have the following DC load line: Now suppose that an AC signal is applied to the input of the transistor. Since the AC load line is the same as the DC load line, the Q point will move up and down on the DC load line. The amplitude of this oscillation depends on the base current of the input signal: The purple waveform shows the input base current change caused by the input signal. It oscillates from approximately 7uA to 17uA. This input causes an output signal from 3 to 11 Volts at VCE (orange waveform). Now suppose that the input signal amplitude is further increased:  A B-Class amplifier clips one complete semi-period of the input signal

As you see, the right side of the output waveform is clipped. We call this "distortion" because the output signal is distorted. In some situations, this distortion is legitimate. A B-Class audio amplifier for example has the Q point very close to one end of the load line, and it amplifies only one side of the input waveform. But there are many situations where the signal must be amplified without any distortion. So, extra care must be taken to avoid clipping.

It is obvious that the maximum output voltage depends on the position of the operating point Q and the maximum VCE. The maximum total VCE oscillation cannot exceed the maximum VCE as defined from the load line. But this is not enough. As you can see, the output waveform could be clipped only in one side. Therefore, we need to define two different maximum levels. Since the output waveform oscillates around the VCEQ point, we divide it into the left portion and the right portion relative to the VCEQ point: VMax-Left = VCEQ
VMax-Right = VCE(cut) - VCEQ

It is obvious that the maximum output can be achieved if the operating point is placed in the middle of VCE. As a matter of fact, the maximum output is achieved if the Q point is little above the middle of VCE, due to the saturation region.

In the previous pages we explained how the load line is affected when load is connected at the transistor output. Moreover, we explained how to draw the AC load line along with the DC load line. I will use the drawing from the final AC-DC load lines from the example in page Drawing the DC and AC load line example. The red line is the DC load line and the green is the AC load line. Both lines intersect at the Q point. The VCE oscillation will still take place around the VCEQ point. It is obvious that the maximum left change is the same like before, without any load being connected at the output. But the maximum right change is now different. Since the cutoff VCE of the AC load line occurs before the cutoff VCE of the DC line, the output signal will be clipped at the AC VCE(cut).

VMax-Left = VCEQ
VMax-Right = VCE(cut)AC - VCEQ

There is a simpler way to calculate the VMax-Right. As we know, the VCE(cut)AC is:

VCE(cut)AC = VCEQ + ICQ x rc

If we replace this equation to the previous, the result is the following:

VMax-Right = ICQ x rc

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